FVUtils is a collection of open-source tools designed for functional verification engineers and developers. From constrained-random stimulus generation to coverage analysis, transaction tracing to HDL integration, FVUtils provides modern, Python-centric solutions for today's verification challenges.
Production-ready tools for verification engineers working on design verification, stimulus generation, and coverage analysis.
Python Verification Stimulus and Coverage
A Python library for verification stimulus and coverage, bringing SystemVerilog-style constrained-random and functional coverage capabilities to Python-based verification environments.
Python Interface for HDL Simulators
Seamless integration between Python and SystemVerilog. Run async pytest tests from SystemVerilog testbenches, call SV functions from Python, and pass structured data using ctypes.Structure. Perfect for modern Python-based verification flows.
Python API to UCIS Coverage Data
Python API for reading and manipulating Unified Coverage Interoperability Standard (UCIS) data. Enables programmatic access to coverage databases from any UCIS-compliant tool.
Qt-based UCIS Coverage Viewer
A desktop application for viewing and analyzing UCIS coverage data. Browse coverage hierarchies, analyze metrics, and visualize results from any UCIS-compliant simulator.
IP and Verification Package Manager
A Python and Git-centric package manager for managing external project dependencies. Originally designed for hardware design, it works with any Git-based project.
Waveform Analysis via Model Context Protocol
MCP server enabling LLM agents to analyze digital waveform files (VCD, FST, GHW) using natural language queries. Features 35+ tools for signal analysis, pattern detection, and waveform export.
Transaction Logging with Perfetto
SystemVerilog and Python bindings for writing transactional data to Perfetto traces. Visualize transaction-level activity from your verification environment using Google's Perfetto UI.
Infrastructure and build tools for developers creating verification environments and EDA workflows.
Dynamic Device Model Loading for QEMU
Research and documentation for loading QEMU device models as dynamically loaded shared libraries. Includes working examples, design documentation, and best practices for extending QEMU without recompilation.
SystemVerilog Dependency Management
A dependency management tool for SystemVerilog that tracks when files have been modified, enabling incremental builds and optimized compilation workflows.
EDA Filelist Utilities
Utilities for parsing and manipulating EDA tool filelists. Handles relative paths, comments, duplicate detection, and common filelist formats used across the EDA ecosystem.
Welcome to the newly redesigned FVUtils organization website! We’ve updated the site to provide a better overview of all the tools and utilities available in the FVUtils ecosystem.
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