Simulator Integration
SystemVerilog (DPI)
Source
The PyHDL-IF SystemVerilog package must be compiled prior to compilation of code that uses PyHDL-IF artifacts. If you use a FuseSoC-based build system, simply place a dependency on fvutils::pyhdl-if.
If you directly specify sources: - Obtain the share directory by calling: python3 -c “import hdl_if; print(hdl_if.share())” - Specify ${share}/dpi as an include directory - Specify ${share}/dpi/pyhdl_if.sv as a source file
Verilog (VPI)
TBD
VHDL (VHPI)
TBD
VHDL (FLI)
TBD